This invention relates generally to a semiconductor integrated circuit device (IC), and more particularly to a technique suitable for use in gate arrays as a type of semi-custom IC.
A gate array includes, for example, an input-output buffer portion and an internal circuit portion, with a plurality of unit cells (macrocells) formed inside the internal circuit portion. Each of the unit cells (macrocells) in turn consists of a plurality of gates.
The gate array makes it possible to produce a wide variety of semiconductor integrated circuit devices by applying respective wirings in accordance with the types of the semiconductor integrated circuit devices to large quantities of master wafers that are produced in advance. The gate array provides other advantages such as the reduction of cost of production due to the mass-production of the master wafers, the automatic design of the wirings, and the reduction of the development period by a production process which requires only wiring.
The term "gate" hereby means a minimum unit constituting a logic circuit (a logical functional block that cannot be divided any more), and the term "unit cell (macrocell)" means a logical functional block constituted by a plurality of gates, such as a multiplexor, a flip-flop, and the like.
The disposition of each cell and the disposition of wirings in the gate array are made by use of CAD (Computer Aided Design) or DA (Design Automation).
Hitachi, Ltd. previously developed a Bi-CMOS gate array of a type in which bipolar elements and CMOSFET (complementary insulated gate field effect transistor) exist inside one chip. This previous arrangement is described in Japanese Patent Application No. 152886/1984. The present invention pertains primarily to improve the integration density of the Bi-CMOS gate array described above and to a layout technique which can enhance the cell utilization efficiency of the gate array.
In order to improve the integration density of the gate array, the following requirements must be satisfied.
(1) A greater number of basic cells (which will be later described) must be formed inside a limited semiconductor substrate.
(2) All the basic cells must be used efficiently.
In the Bi-CMOS composite gate array described above, however, it has been difficult to satisfy the requirements (1) and (2) described above because the area of one basic cell tends to be greater than that of a pure CMOS cell, and to secure wiring regions.